Hardware-Aware ML

DRACO: Co-Optimizing Hardware Utilization and Performance of DNNs on Systolic Accelerator
Co-optimizes DNN structure for systolic accelerators, improving hardware utilization, inference latency, and energy efficiency without requiring hardware dataflow changes.
Nandan Kumar Jha, Shreyas Ravishankar, Sparsh Mittal, Arvind Kaushik, Dipan Mandal, Mahesh Chandra
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DRACO: Co-Optimizing Hardware Utilization and Performance of DNNs on Systolic Accelerator